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ispLSI 2192VL
2.5V In-System Programmable SuperFASTTM High Density PLD Features
* SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 8000 PLD Gates 96 I/O Pins, Nine Dedicated Inputs 192 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic -- Pinout Compatible with ispLSI 2096V and 2096VE * 2.5V LOW VOLTAGE ARCHITECTURE -- Interfaces with Standard 3.3V Devices (Inputs and I/Os are 3.3V Tolerant) -- 175 mA Typical Active Current * HIGH PERFORMANCE E CMOS TECHNOLOGY -- -- -- -- -- --
2 (R)
(R)
Functional Block Diagram
Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 A0
Output Routing Pool
Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 D7 D5
Output Routing Pool
DQ
-- -- -- -- --
A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool
D6
Logic
DQ
Global Routing Pool (GRP)
Array
DQ
GLB
D4 D3 D2 D1 D0
DQ
C0 C1 C2 C3 C4 C5 C6 C7 Output Routing Pool
fmax = 150 MHz Maximum Operating Frequency tpd = 6.0 ns Propagation Delay
Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power
Description
The ispLSI 2192VL is a High Density Programmable Logic Device containing 192 Registers, nine Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2192VL features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2192VL offers nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2192VL device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. F7 (see Figure 1). There are a total of 48 GLBs in the ispLSI 2192VL device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
* IN-SYSTEM PROGRAMMABLE -- 2.5V In-System Programmability (ISPTM) Using Boundary Scan Test Access Port (TAP) -- Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of WiredOR Bus Arbitration Logic -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping * 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE * THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS -- -- -- -- -- -- Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity
* ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms
Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2192vl_02
1
CLK0 CLK1 CLK2
0139/2192VL
Specifications ispLSI 2192VL
Functional Block Diagram
Figure 1. ispLSI 2192VL Functional Block Diagram
I/O I/O I/O I/O 95 94 93 92 RESET
GOE 0 GOE 1
I/O I/O I/O I/O 91 90 89 88
I/O I/O I/O I/O 87 86 85 84
I/O I/O I/O I/O 83 82 81 80
IN IN 11* 10
I/O I/O I/O I/O 79 78 77 76
I/O I/O I/O I/O 75 74 73 72
I/O I/O I/O I/O 71 70 69 68
I/O I/O I/O I/O 67 66 65 64
IN 9
IN 8
Input Bus Generic Logic Blocks (GLBs) F7 F6 Output Routing Pool (ORP) F5 F4 F3 F2 F1 F0 E7 E6
Input Bus Output Routing Pool (ORP) E5 E4 E3 E2 E1 E0
IN 7/TCK IN 6/TDO I/O 63 I/O 62 I/O 61 I/O 60
D7
I/O 0 I/O 1 I/O 2 I/O 3
A0 A1
D6
Output Routing Pool (ORP)
D5
I/O 59 I/O 58 I/O 57
Output Routing Pool (ORP)
D4 D3 D2 D1 D0
lnput Bus
Input Bus
I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 TDI/IN 0 TMS/IN 1
A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7
Global Routing Pool (GRP)
I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48
CLK 0
CLK 1
Output Routing Pool (ORP) Megablock Input Bus
BSCAN
IN 2* IN 3
Output Routing Pool (ORP) Input Bus
I/O I/O I/O I/O 16 17 18 19
I/O I/O I/O I/O 20 21 22 23
I/O I/O I/O I/O 24 25 26 27
I/O I/O I/O I/O 28 29 30 31
IN4 IN 5*
I/O I/O I/O I/O 32 33 34 35
I/O I/O I/O I/O 36 37 38 39
I/O I/O I/O I/O 40 41 42 43
I/O I/O I/O I/O 44 45 46 47
Y0 Y1 Y2
*Note: Dedicated Inputs 2, 5 and 11 are not available with 128-pin packages.
2192VL Block.eps
The 2192VL contains 96 I/O cells. Each I/O cell is directly connected to an I/O pin and can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control, and the output drivers can source 4mA or sink 8mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 3.3V signal levels to support mixed-voltage systems. Eight GLBs, 16 I/O cells, two dedicated inputs and an ORP are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORPs. Each ispLSI 2192VL device contains six Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew.
Clocks in the ispLSI 2192VL device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2192VL are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration is a totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.
2
CLK 2
C0
C1
C2
C3
C4
C5
C6
C7
Specifications ispLSI 2192VL
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................ -0.5 to +4.05V Input Voltage Applied ............................. -0.5 to +4.05V Off-State Output Voltage Applied .......... -0.5 to +4.05V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial TA = 0C to + 70C TA = -40C to + 85C MIN. 3.0 3.0 VSS -- 0.5 2.0 MAX. 3.6 3.6 0.8 5.25 UNITS V V V V
VCC VIL VIH
Table 2-0005/2192VL
Capacitance (TA=25C, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input Capacitance I/O Capacitance Clock and Global Output Enable Capacitance TYPICAL 8 6 10 UNITS pf pf pf TEST CONDITIONS VCC = 2.5V, VIN = 0.0V VCC = 2.5V, VI/O = 0.0V VCC = 2.5V, VY = 0.0V
Table 2-0006/2192VL
C1 C2 C3
Erase Reprogram Specifications
PARAMETER Erase/Reprogram Cycles MINIMUM 10,000 MAXIMUM -- UNITS Cycles
Table 2-0008/2192VL
3
Specifications ispLSI 2192VL
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load
3-state levels are measured 0.15V from steady-state active level.
GND to VCC 1.5ns 10% to 90% VCC/2 VCC/2 See Figure 2
Table 2 - 0003/2192VL
Figure 2. Test Load
VCC R1 Device Output R2 CL* Test Point
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.15V Active Low to Z at VOL +0.15V R1 250 R2 218 218 CL 35pF 35pF 35pF 5pF 5pF
250
*CL includes Test Fixture and Probe Capacitance.
0213A/2192VL
218
250
C
Table 2-0004/2192VL
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Low Voltage CONDITION IOL = 100A IOL = 8mA IOH = -100A Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current BSCAN Input Pull-Up Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOH = -1mA IOH = -4mA 0V VIN VIL (Max.) VIH (min) VIN 3.6V 0V VIN VIL 0V VIN VIL VCC = 2.5V, VOUT = 0.5V VIL = 0.0V, VIH = 2.5V fCLK = 1 MHz
Table 2-0007/2192VL 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using 12 16-bit counters. 3. Typical values are at VCC = 2.5V and TA = 25C. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC. 5. With no pull-up resistors.
MIN. -- --
VCC - 0.2
TYP. -- -- -- -- -- -- -- -- -- -- 175
3
MAX. UNITS 0.2 0.4 -- -- -- -10 10 -150 -150 -100 -- V V V V V A A A A mA mA
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4
5
2.0 1.8 -- -- -- -- -- --
4
Specifications ispLSI 2192VL
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND. A A A -- -- -- A -- -- A -- A -- B C B C -- --
3
# 1 2 3 4 5 6 7 8 9
DESCRIPTION
1
-150 -- --
2 1
-135 -- -- 135 95 143 5.0 -- 0.0 6.0 -- 0.0 -- 5.5 -- -- -- -- 3.5 3.5 7.5 10.0 -- -- -- -- 4.5 -- -- 5.5 -- 8.0 -- 12.0 12.0 7.0 7.0 -- --
-100 -- -- 100 77 100 6.5 -- 0.0 8.0 -- 0.0 -- 6.5 -- -- -- -- 5.0 5.0 10.0 13.0 -- -- -- -- 5.0 -- -- 6.0 -- 13.5 -- 15.0 15.0 9.0 9.0 -- --
MIN. MAX. MIN. MAX. MIN. MAX. 6.0 8.5 -- -- -- -- 4.0 -- -- 5.0 -- 6.0 -- 10.0 10.0 6.0 6.0 -- --
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle GLB Reg. Setup Time before Clock, 4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock Clock Frequency with External Feedback ( tsu2 + tco1)
150 111 166 4.0 -- 0.0 5.0 -- 0.0 -- 5.0 -- -- -- -- 3.0 3.0
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay, ORP Bypass 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section.
Table 2-0030C/2192VL
5
Specifications ispLSI 2192VL
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Inputs #
2
DESCRIPTION
-150
-135
-100
MIN. MAX. MIN. MAX. MIN. MAX. -- -- -- -- -- -- -- -- -- 1.2 2.8 -- -- -- -- 1.2 -- -- -- -- -- -- -- 1.7 1.9 -- 0.4 1.5 1.1 2.5 3.0 4.0 4.0 4.0 0.0 -- -- 0.3 0.6 4.9 5.0 4.2 1.4 0.4 1.6 2.0 3.5 3.5 2.5 1.7 1.9 3.4 -- -- -- -- -- -- -- -- -- 1.7 3.3 -- -- -- -- 2.1 -- -- -- -- -- -- -- 2.1 2.3 -- 1.0 2.2 1.2 3.2 3.2 4.2 4.2 4.2 0.5 -- -- 0.3 1.1 6.6 5.8 4.5 1.5 0.5 1.6 2.0 4.0 4.0 3.0 2.1 2.3 4.8 -- -- -- -- -- -- -- -- -- 1.7 4.8 -- -- -- -- 2.8 -- -- -- -- -- -- -- 2.6 2.8 -- 0.9 2.7 1.8 5.2 4.7 6.2 6.2 6.2 1.0 -- -- 0.3 4.3 8.9 7.4 4.8 1.5 0.5 1.6 2.0 4.9 4.9 4.1 2.6 2.8 7.1
UNITS
tio tdin
GRP
20 Input Buffer Delay 21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay 3 28 GLB Register Bypass Delay 29 GLB Register Setup Time before Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay 33 GLB Product Term Reset to Register Delay 34 GLB Product Term Output Enable to I/O Cell Delay 35 GLB Product Term Clock Delay 36 ORP Delay 37 ORP Bypass Delay 38 Output Buffer Delay 39 Output Slew Limited Delay Adder 40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled 42 Global Output Enable 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 45 Global Reset to GLB
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp
GLB
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
torp torpbp
Outputs
tob tsl toen todis tgoe
Clocks
tgy0 tgy1/2
Global Reset
tgr
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036/2192VL
6
Specifications ispLSI 2192VL
ispLSI 2192VL Timing Model
I/O Cell GRP Feedback Ded. In Comb 4 PT Bypass #23 GRP #22 Reg 4 PT Bypass #24 20 PT XOR Delays #25, 26, 27 Reset #45 D RST #29, 30, 31, 32 GLB Reg Bypass #28 GLB Reg Delay Q ORP Bypass #37 ORP Delay #36 #38, 39 I/O Pin (Output) GLB ORP I/O Cell
#21 I/O Delay #20
I/O Pin (Input)
Control RE PTs OE #33, 34, CK 35 Y0,1,2 GOE 0 #43, 44 #42
#40, 41
0491/2032
Derivations of tsu, th and tco from the Product Term Clock tsu
= = = 4.0ns = = = = 3.0ns = = = = 9.0ns = Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.4 + 1.1 + 4.0) + (1.2) - (0.4 + 1.1 + 1.2) Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.4 + 1.1 + 4.2) + (2.8) - (0.4 + 1.1 + 4.0) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.4 + 1.1 + 4.2) + (0.3) + (1.4 + 1.6)
th
tco
Note: Calculations are based upon timing specifications for the ispLSI 2192VL-150L.
Table 2-0042/2192VL
7
Specifications ispLSI 2192VL
Power Consumption
Power consumption in the ispLSI 2192VL device depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax
275
used. Figure 3 shows the relationship between power and operating speed.
ispLSI 2192VL
250 225 200 175 150
0 25 50 75 100 125 150
ICC (mA)
fmax (MHz)
Notes: Configuration of 12 16-bit counters Typical current at 2.5V, 25 C
ICC can be estimated for the ispLSI 2192VL using the following equation: ICC = 12 + (# of PTs * 0.44) + (# of nets * max freq * 0.0029)
Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 2.5V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127/2192VL
8
Specifications ispLSI 2192VL
Signal Descriptions
Signal Name RESET GOE 0, GOE1 Y0, Y1, Y2 BSCAN TDI/IN 0 TCK/IN 7 TMS/IN 1 TDO/IN 6 IN 2-5, IN 8-11 GND VCC NC1 I/O Global Output Enable input pins. Dedicated Clock Input - These clock inputs are connected to one of the clock inputs of all the GLBs in the device. Input - Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input - This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Output/Input - This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Dedicated Input Pins to the device. Ground (GND) Vcc No Connect Input/Output Pins - These are the general purpose I/O pins used by the logic array. Description Active Low (0) Reset pin resets all the registers in the device.
1. NC pins are not to be connected to any active signals, VCC or GND.
Signal Locations
Signal Name RESET GOE 0, GOE 1 Y0, Y1, Y2 BSCAN TDI/IN 0 TMS/IN 1 TDO/IN 6 TCK/IN 7 IN 2-5, IN 8-11 GND 15 80, 17 14, 83, 78 19 20 112 48 77 128-Pin TQFP G4 F12, G2 F3, F10, G11 F1 G3 J6 C7 G12 144-Ball fpBGA
--, 49, 82, --, 84, 113, 13, -- M7, J7, F9, G10, E12, B6, F2, E1 18, 34, 50, 63, 79, 98, 111, 127 2, 16, 31, 47, 66, 81, 95, 114 -- A1, A12, D4, D9, E5, E8, F6, F7, G6, G7, H5, H8, J4, J9, M1, M12 B1, B12, E6, E7, F5, F8, G5, G8, H6, H7, L1, L12 K2
VCC NC1
1. NC pins are not to be connected to any active signals, VCC or GND.
9
Specifications ispLSI 2192VL
I/O Locations
Signal 128 TQFP 144 fpBGA Signal 128 TQFP 144 fpBGA
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47
21 22 23 24 25 26 27 28 29 30 32 33 35 36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55 56 57 58 59 60 61 62 64 65 67 68 69 70 71 72 73 74 75 76
H4 G1 H2 H1 H3 J1 J3 K1 J2 M2 L2 L3 K3 M3 L4 K4 M4 J5 M5 K5 L5 M6 L6 K6 L7 K7 J8 M8 L8 K8 M9 L9 K9 M10 L10 M11 K10 K11 L11 K12 J11 J12 J10 H9 H11 H12 H10 G9
I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 I/O 75 I/O 76 I/O 77 I/O 78 I/O 79 I/O 80 I/O 81 I/O 82 I/O 83 I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95
85 86 87 88 89 90 91 92 93 94 96 97 99 100 101 102 103 104 105 106 107 108 109 110 115 116 117 118 119 120 121 122 123 124 125 126 128 1 3 4 5 6 7 8 9 10 11 12
F11 D12 E9 E10 E11 C12 D10 D11 B11 C11 C10 A11 B10 A10 C9 B9 A9 D8 B8 C8 A8 B7 A7 D7 C6 A6 D6 B5 C5 A5 D5 C4 B4 A4 C3 B3 A3 C2 B2 D2 A2 D3 E2 C1 E3 E4 D1 F4
10
Specifications ispLSI 2192VL
Pin Configuration
ispLSI 2192VL 128-Pin TQFP Pinout Diagram
I/O 84 GND I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 VCC IN 9 TDO/IN 6 GND I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND I/O 59 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
I/O 85 VCC I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 IN10 Y0 RESET VCC GOE 1 GND BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 VCC I/O 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ispLSI 2192VL
Top View
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
I/O 58 VCC I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 8 Y1 IN4 VCC GOE 0 GND Y2 TCK/IN 7 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 VCC I/O 37
I/O 11 GND I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 VCC TMS/IN 1 IN3 GND I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 GND I/O 36
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
0124-2192VL
11
Specifications ispLSI 2192VL
Pin Configuration
ispLSI 2192VL 144-Ball fpBGA Signal Diagram
12 A B C D E F G H J K L M
GND
11
I/O 59 I/O 56 I/O 57 I/O 55 I/O 52 I/O 48 Y2 I/O 44 I/O 40 I/O 37 I/O 38 I/O 35
10
I/O 61 I/O 60 I/O 58 I/O 54 I/O 51 Y1
9
I/O 64 I/O 63 I/O 62 GND I/O 50 IN 4 I/O 47 I/O 43 GND I/O 32 I/O 31 I/O 30
8
I/O 68 I/O 66 I/O 67 I/O 65 GND
7
I/O 70 I/O 69 TDO/ IN 6 I/O 71 VCC
6
I/O 73 IN 9 I/O 72 I/O 74 VCC
5
I/O 77 I/O 75 I/O 76 I/O 78 GND
4
I/O 81 I/O 80 I/O 79 GND I/O 93 I/O 95
RESET
3
I/O 84 I/O 83 I/O 82 I/O 89 I/O 92 Y0 TDI/ IN 0 I/O 4 I/O 6 I/O 12 I/O 11 I/O 13
2
I/O 88 I/O 86 I/O 85 I/O 87 I/O 90
1
GND
A B C D E F G H J K L M
VCC I/O 53 I/O 49 IN 8 GOE 0 TCK/ IN 7 I/O 45 I/O 41 I/O 39 VCC
VCC I/O 91 I/O 94 IN 11
VCC
GND
GND
VCC
IN 10 BSCAN I/O 1 I/O 3 I/O 5 I/O 7 VCC
IN 5 I/O 46 I/O 42 I/O 36 I/O 34 I/O 33
VCC
GND
GND
VCC
GOE 1 I/O 2 I/O 8 NC1 I/O 10 I/O 9
GND I/O 26 I/O 29 I/O 28 I/O 27
VCC
VCC TMS/ IN 1 I/O 23 I/O 22 I/O 21
GND I/O 17 I/O 19 I/O 20 I/O 18
I/O 0 GND I/O 15 I/O 14 I/O 16
IN 3 I/O 25 I/O 24 IN 2
GND
GND
12
11
10
9
8
7
6
5
4
3
2
1
144-BGA/2192VL
ispLSI 2192VL
Bottom View
1NCs
are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
12
Specifications ispLSI 2192VL
Part Number Description
ispLSI 2192VL - XXX X
Device Family Device Number Speed 150 = 150 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax
XXXX X
Grade Blank = Commercial Package T128 = 128-Pin TQFP B144 = 144-Ball fpBGA Power L = Low
0212A/2192VL
ispLSI 2192VL Ordering Information
COMMERCIAL
FAMILY fmax (MHz) 150 150 ispLSI 135 135 100 100 tpd (ns) 6.0 6.0 7.5 7.5 10 10 ORDERING NUMBER ispLSI 2192VL-150LT128 ispLSI 2192VL-150LB144 ispLSI 2192VL-135LT128 ispLSI 2192VL-135LB144 ispLSI 2192VL-100LT128 ispLSI 2192VL-100LB144 PACKAGE 128-Pin TQFP 144-Ball fpBGA 128-Pin TQFP 144-Ball fpBGA 128-Pin TQFP 144-Ball fpBGA
Table 2-0041C/2192VL
13

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